A phase locked loop is a well known circuit which typically includes a phase detector, a filter, and a voltage controlled oscillator (VCO). A stable input signal or reference signal is applied to the phase detector which compares the input signal to the output of the voltage controlled oscillator. The output signal of the phase detector is representative of the phase difference between the input signal and the output signal of the voltage controlled oscillator. The output signal of the phase detector is filtered. The filtered signal is then used as an error signal to control the voltage controlled oscillator, thereby causing the frequency of the voltage controlled oscillator to track the frequency of the stable input signal.
It is well known to those skilled in the art to generate different signals having a carefully determined frequency f.sub.vco using a frequency synthesizer having a PLL 10 as illustrated in FIG. 1. The PLL 10 includes a controllable oscillator VCO 14 which is locked to a crystal source which provides an input signal f.sub.xtal. The frequency of the VCO signal f.sub.vco is typically divided by a controllable divider 15 having a division number N to obtain a signal having a frequency f.sub.v. The signal f.sub.v is thereafter compared to the reference signal f.sub.ref which is derived from the division of the input signal f.sub.xtal from the crystal frequency source by a frequency divider 11 having a division number R. The comparison of the signals having frequencies f.sub.ref and f.sub.v in the phase detector 12 generates the control or error signal E. The control signal E is filtered by the filter 13 in order to remove signal components emanating from the signals f.sub.ref and f.sub.v respectively. The filtered signal U controls the VCO 14 so that a balanced condition is reached (f.sub.vco =f.sub.xtal .times.N.div.R). By choosing different division numbers, N and R respectively, different frequencies can be achieved with a relatively high degree of accuracy.
In this type of frequency synthesizer, the frequency can be changed by selecting the division numbers R and N. After a new frequency has been selected, a certain time is required to achieve a balanced condition. The amount of time is usually dependent upon the filter 13. In many implementations, it is necessary to quickly achieve a stable output signal f.sub.vco. Accordingly, the filter 13 has to be designed to have a relatively broad bandwidth.
The bandwidth of the filter 13 in relation to the reference frequency f.sub.ref also determines how large a disturbance from f.sub.ref and f.sub.v will leak through to the VCO 14. Consequently, the filter 13 and the reference frequency f.sub.ref determine the level of disturbances in the VCO output signal f.sub.vco. The smallest channel spacing needs to be equal to or larger than the reference frequency f.sub.ref. The requirements for a pure signal, therefore, are in conflict with the requirements for a relatively quick locked-in and relatively tight channel spacing.
In order to solve this conflict, a known solution is to switch the bandwidth of the phase locked loop during the locked-in process. As soon as the phase locked loop acquires a locked condition, or a small phase error is attained, the bandwidth is changed from a relatively broad value to a narrow one. The above-described method, however, has certain drawbacks. The switching instant has to be decided, and equipment to make such a decision and the switching itself as well as switchable loop filter have to be implemented. Other methods are also known, e.g., presetting the voltage in the filter controlling the VCO. Most of these methods result in extra components which are needed to speed up the phase locked loop locked-in process and to keep the loop narrow during the locked state. Accordingly, there is a need for a new phase locked loop which can achieve quick locked-in combined with a low disturbance level without adding a lot of extra components to the system.
Another problem with conventional frequency synthesizers is that components of the frequency synthesizer may need to be trimmed. Since some parameters of a phase locked loop are not always accurately known, the transfer function of the frequency synthesizer is difficult to accurately predict. As a result, components of the phase locked loop, like capacitors, may need to be trimmed, which can be an expensive procedure, in order to optimalize the performance of the frequency synthesizer. Accordingly, there is a need for a frequency synthesizer which does not need to be trimmed in order to obtain optimal performance.